To debug the SVNES system, a separate 6502 core was added.
It can directly write to part of SDRAM region, for output text to the TFT frame buffer.
The system bus and register inspections were done by using a parallel-to-serial shift-register-based data transfer interface, much like SPI/74xx595. Interface signals: load, shift, din, dout
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[youtube https://youtu.be/2E9pHYqWlOU\]
